(a) Field of the invention
The present invention relates to an FM stereophonic receiver having a built-in central processing unit, and more particularly, it pertains to an FM stereophonic receiver having a central processing unit intended primarily for the selection of broadcasting stations and also for being used concurrently for the purpose of multiplex demodulation.
(b) Description of the prior art
FIG. 1 is a block diagram showing an example of a conventional FM stereophonic receiver provided with a built-in central processing unit (which will hereinafter be referred to briefly as CPU). In FIG. 1, an FM broadcast signal which is inputted through an antenna 1 is subjected to high frequency amplification at a front-end 2, and concurrently therewith, it is converted to IF (intermediate frequency) signal, and furthermore, it is submitted to IF amplification as well as to FM detection through an IF amplifier-FM detector circuit 3, to be derived as a composite signal containing a right-channel and a left-channel stereophonic signal and a pilot signal (i.e. a main-channel signal, a sub-channel signal and a pilot signal). Then, this composite signal is demodulated into a left-channel signal L.sub.0 and a right-channel signal R.sub.0 through a multiplex demodulator circuit 4. Further therefrom, these left and right-channel signals L.sub.0 and R.sub.0 are derived at a left-channel output terminal OUT(L) and a right-channel output terminal OUT(R) via respective low frequency amplifier circuits 5L and 5R and via respective muting gates 6L and 6R. On the other hand, a tuning PLL (Phase-locked Loop) section 7 is comprised of a PLL circuit which carries out a PLL behavior based on a reference tuning frequency, in accordance with the frequency dividing data supplied from a CPU 8, to thereby generate a tuning controlling voltage V.sub.T. This tuning PLL section 7, after a tuning is once established, will maintain a certain broadcast reception based on the then-supplied frequency-dividing data, as this section 7 receives an S-curve signal V.sub.S from the IF amplifier-FM detector circuit 3. In other words, the tuning controlling voltage V.sub.T outputted from the tuning PLL section 7 is supplied to the front-end 2. By this tuning controlling voltage V.sub.T, the tuning varicap diode of a high frequency amplifier circuit and a voltage-controlled oscillator (VCO) of the local oscillator circuit are controlled, and thus a station-selection is carried out. And, after the establishment of tuning, the then tuning controlling voltage V.sub.T is locked, and thus the receiving frequency at such time is locked accordingly.
The CPU 8 is so constructed that it is controlled of its program-running rate by a certain constant clock signal generated by a quartz oscillator circuit 21, and performs controlling of selection of various broadcasting stations, such as preset tuning controlling and auto-tuning controlling, in accordance with the manipulation of various switches provided on an operating panel 9, and that concurrently therewith, it also supplies such data as receiving frequency data to a frequency indicator 10, and it controls the ON/OFF of the muting gates 6L and 6R so as to cause them to be off only at the time of "out of tune".
And, the detection of tuning condition by an auto-tuning control system is carried out based on the output of the S-curve signal V.sub.s which is delivered from the IF amplifier-FM detector circuit 3.
On the other hand, sub-carrier signals .phi..sub.1 and .phi..sub.2 (38 kHz, .phi..sub.1 =.phi..sub.2) which are necessary for the multiplex demodulation conducted in the multiplex demodulator circuit 4 are formed by a PLL circuit 11. This PLL circuit 11 is constructed by a phase-comparator circuit (hereinafter referred to breifly as PC) 14 for carrying out a comparison of phases between a pilot signal (19 kHz) derived from the composite signal via a band-pass filter (hereinafter referred to briefly as BPF) 12 and an output of a frequency divider circuit (hereinafter referred to briefly as DIV) 13 (which output is a signal obtained after dividing, into one half, sub-carrier signal .phi..sub.1 or .phi..sub.2), a VCO 15 for oscillating at 76 kHz when a phase-matching is detected by said PC 14, and a DIV 16 for dividing, into one half, the output frequency of this VCO 15 to form the sub-carrier signals .phi..sub.1 and .phi..sub.2 of 38 kHz, respectively.
Also, as for the discrimination of a stereophonic signal from a monaural signal, such discrimination is accomplished in a manner that the signal frequency of said sub-carrier-forming DIV 16 is subjected to a further division into one half by another DIV 17 to derive a signal .phi..sub.3 (19 kHz) which is synchronous with the pilot signal, and that the composite signal is introduced into a synchronous detector circuit 18 for carrying out a synchronous detection by utilizing said signal .phi..sub.3, and that the resulting 19 kHz component thus obtained is subjected to level discrimination at a monaural-stereo detector circuit 19, to drive a stereo-indicator 20 by an output of said detector circuit 19.
However, in the conventional FM stereophonic receiver using a central processing unit, there exist a number of sources of oscillation which individually oscillate signals in non-synchronous conditions relative to each other. Thus, there could often arise mutual interferences therebetween. Especially, owing to the interference occurring between the CPU-controlling clock pulse delivered from the quartz oscillator circuit 21 and the oscillation signal of the VCO 15 which is provided in the PLL circuit 11, there are often introduced noises into the sub-carrier signals .phi..sub.1 and .phi..sub.2, resulting in the degradation of the signal-to-noise ratio of the left-channel signal L.sub.0 and the right-channel signal R.sub.0 outputted from the multiplex demodualtor circuit 4.
Also, a conventional central processing unit which has been heretofore used for the purpose of controlling the selection of broadcasting stations operates in such manner that, once a tuning is established, it will output certain frequency-division data as stated above. Thus, unless re-tuning is established or a next operation is started, the required functions of this central processing unit will become limited thereto.
However, for example, if the operation is set so that, following the completion of tuning, the frequency-division data are stored in such section as a buffer memory, and that, after the tuning is established, the CPU is caused to function so as to extract a pilot signal which has conventionally been obtained by an exclusively-assigned PLL circuit 11, such arrangement of operation will result in a markedly efficient utilization of the CPU. Also, during non-tuned period (non-locked period), there is required no function of extracting pilot signal, and therefore, the CPU can concentrate a part of its functions only to the selection of broadcasting stations. The primary function of the CPU will never be impaired by the addition of said function to extract a pilot signal.